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a
Single and Multichannel, Synchronous Voltage-to-Frequency Converters AD7741/AD7742
FUNCTIONAL BLOCK DIAGRAMS
VDD REFIN/OUT PD +2.5V REFERENCE
FEATURES AD7741: One Single-Ended Input Channel AD7742: Two Differential or Three Pseudo-Differential Input Channels Integral Nonlinearity of 0.012% at fOUT(Max) = 2.75 MHz (AD7742) and at fOUT(Max) = 1.35 MHz (AD7741) Single +5 V Supply Operation Buffered Inputs Programmable Gain Analog Front-End On-Chip +2.5 V Reference Internal/External Reference Option Power Down to 35 A Max Minimal External Components Required 8-Lead and 16-Lead DIP and SOIC Packages APPLICATIONS Low Cost Analog-to-Digital Conversion Signal Isolation
GAIN VIN1 VIN2 VIN3
POWER-DOWN LOGIC
VIN
X1
VOLTAGE-TOFREQUENCY MODULATOR
fOUT
CLOCK GENERATION
AD7741
CLKIN
CLKOUT
GND
VDD
UNI/BIP
PD
AD7742
POWER-DOWN LOGIC
INPUT MUX
X1/X2
VOLTAGE-TOFREQUENCY MODULATOR
fOUT
GENERAL DESCRIPTION
VIN4 A1 A0 CLOCK GENERATION +2.5V REFERENCE
The AD7741/AD7742 are a new generation of synchronous voltage-to-frequency converters (VFCs). The AD7741 is a single-channel version in an 8-lead package (SOIC/DIP) and the AD7742 is a multichannel version in a 16-lead package (SOIC/ DIP). No user trimming is required to achieve the specified performance. The AD7741 has a single buffered input whereas the AD7742 has four buffered inputs that may be configured as two fullydifferential inputs or three pseudo-differential inputs. Both parts include an on-chip +2.5 V bandgap reference that provides the user with the option of using this internal reference or an external reference.
GND
CLKIN
CLKOUT
REFIN
REFOUT
The AD7741 has a single-ended voltage input range from 0 V to REFIN. The AD7742 has a differential voltage input range from -VREF to +VREF. Both parts operate from a single +5 V supply consuming typically 6 mA, and also contain a powerdown feature that reduces the current consumption to less than 35 A.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD7741-SPECIFICATIONS T
Parameter
2
(VDD = +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to MAX unless otherwise noted.)
Units Conditions/Comments
B and Y Version1 Min Typ Max
DC PERFORMANCE Integral Nonlinearity fCLKIN = 200 kHz3 fCLKIN = 3 MHz3 fCLKIN = 6.144 MHz Offset Error Gain Error Offset Error Drift3 Gain Error Drift3 Power Supply Rejection Ratio3 ANALOG INPUT5 Input Current Input Voltage Range +2.5 V REFERENCE (REFIN/OUT) REFIN Nominal Input Voltage Input Impedance6 REFOUT Output Voltage Output Impedance3 Reference Drift3 Line Rejection Reference Noise (0.1 Hz to 10 Hz)3 LOGIC OUTPUT Output High Voltage, VOH Output Low Voltage, VOL Minimum Output Frequency Maximum Output Frequency LOGIC INPUT PD ONLY Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance CLKIN ONLY Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance CLOCK FREQUENCY Input Frequency POWER REQUIREMENTS VDD IDD (Normal Mode) IDD (Power-Down) Power-Up Time3
0
+0.8 30 16 -63 50
0.012 0.012 0.024 40 +1.6
% of Span4 % of Span % of Span mV % of Span V/C ppm of Span/C dB nA V
VDD > 4.8 V
VDD = 5%
0
100 VREF
2.5 N/A 2.38 2.50 1 50 -60 100 2.60
V
V k ppm/C dB V p-p V V Hz Hz Output Sourcing 800 A7 Output Sinking 1.6 mA7 VIN = 0 V VIN = VREF
4.0 0.4 0.05 fCLKIN 0.45 fCLKIN
2.4 0.8 100 10
6 3.5
V V nA pF V V A pF MHz V mA A s For Specified Performance
6
0.8 2 10 6.144
4.75 15 30
5.25 8 35
Output Unloaded Coming Out of Power-Down Mode
NOTES 1 Temperature ranges: B Version -40C to +85C: Y Version: -40C to +105C. 2 See Terminology. 3 Guaranteed by design and characterization, not production tested. 4 Span = Maximum Output Frequency-Minimum Output Frequency. 5 The absolute voltage on the input pin must not go more positive than V DD - 2.25 V or more negative than GND. 6 Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 A in order to overdrive the internal reference. 7 These logic levels apply to CLKOUT only when it is loaded with one CMOS load. Specifications subject to change without notice.
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AD7741/AD7742
AD7742-SPECIFICATIONS (V T
B Version1
Parameter3 DC PERFORMANCE Integral Nonlinearity fCLKIN = 200 kHz4 fCLKIN = 3 MHz4 fCLKIN = 6.144 MHz Offset Error Gain Error Offset Error Drift 4 Gain Error Drift 4 Power Supply Rejection Ratio 4 Channel-to-Channel Isolation 4 Common-Mode Rejection ANALOG INPUTS (VIN1-VIN4)6 Input Current Common-Mode Input Range Differential Input Range VOLTAGE REFERENCE REFIN Nominal Input Voltage Input Impedance 4 fCLKIN = 3 MHz fCLKIN = 6.144 MHz REFOUT Output Voltage Output Impedance 4 Reference Drift 4 Line Rejection Reference Noise (0.1 Hz to 10 Hz) 4 LOGIC OUTPUT Output High Voltage, V OH Output Low Voltage, VOL Minimum Output Frequency Maximum Output Frequency LOGIC INPUT ALL EXCEPT CLKIN Input High Voltage, V IH Input Low Voltage, V IL Input Current Pin Capacitance CLKIN ONLY Input High Voltage, V IH Input Low Voltage, V IL Input Current Pin Capacitance CLOCK FREQUENCY Input Frequency POWER REQUIREMENTS VDD IDD (Normal Mode) IDD (Power-Down) Power-Up Time 4 NOTES
1 2 3
DD
MAX
= +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to unless otherwise noted.)
Y Version2
Min Typ Max Units Conditions/Comments
Min
Typ
Max
+0.2 +0.2
-60
+1.2 +1.2 12 12 2 4 -70 -75 -78 50
0.0122 0.0122 0.0122 40 40 +2.2 +2.2
+0.2 +0.2
-58 100 VDD - 1.75 +0.5 +VREF/Gain -VREF/Gain +VREF/Gain 0
+1.2 +1.2 12 12 2 4 -70 -75 -78 50
0.015 0.015 0.015 40 40 +2.2 +2.2
% of Span 5 % of Span % of Span mV mV % of Span % of Span V/C V/C ppm of Span/C ppm of Span/C dB dB dB nA V V V
Unipolar Mode Bipolar Mode Unipolar Mode Bipolar Mode Unipolar Mode Bipolar Mode Unipolar Mode Bipolar Mode VDD = 5%
+0.5 -VREF/Gain 0
100 VDD - 1.75 +VREF/Gain +VREF/Gain
Bipolar Mode Unipolar Mode
2.5 70 35 2.38 2.50 1 50 -70 100 4.0 0.4 0.05 fCLKIN 0.45 fCLKIN 4.0 2.60 70 35 2.38
2.5
V k k
2.50 1 50 -70 100
2.60
V k ppm/C dB V p-p V V Hz Hz Output Sourcing 800 A7 Output Sinking 1.6 mA7 VIN = 0 V (Unipolar), VIN = -VREF/Gain (Bipolar) VIN = VREF/Gain (Unipolar and Bipolar)
0.4 0.05 fCLKIN 0.45 fCLKIN
2.4 0.8 100 10
2.4 0.8 100 10
6 3.5
6 3.5
V V nA pF V V A pF MHz V mA A s For Specified Performance
6
0.8 2 10 6.144
6
0.8 2 10 6.144
4.75 6 25 30
5.25 8 35
4.75 6 25 30
5.25 8 35
Output Unloaded Coming Out of PowerDown Mode
Temperature range: B Version: -40C to +85C. Temperature range: Y Version: -40C to +105C. See Terminology. 4 Guaranteed by design and characterization, not production tested. 5 Span = Maximum Output Frequency-Minimum Output Frequency. 6 The absolute voltage on the input pins must not go more positive than V DD - 1.75 V or more negative than +0.5 V. 7 These logic levels apply to CLKOUT only when it is loaded with one CMOS load. Specifications subject to change without notice.
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AD7741/AD7742 TIMING CHARACTERISTICS1, 2, 3 (V
Parameter fCLKIN tHIGH/tLOW t1 t2 t3 t4 Limit at TMIN, TMAX (B and Y Version) 6.144 55/45 45/55 9 4 4 tHIGH 5
DD
= +4.75 V to +5.25 V; VREF = +2.5 V. All specifications TMIN to TMAX unless otherwise noted.)
Units MHz max max min ns typ ns typ ns typ ns typ Conditions/Comments Input Clock Mark/Space Ratio fCLOCK Rising Edge to fOUT Rising Edge fOUT Rise Time fOUT Fall Time fOUT Pulsewidth
NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 See Figure 1. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1, 2
tHIGH
CLKIN
(TA = +25C unless otherwise noted)
t4
fOUT
t1
t2
t3
Figure 1. Timing Diagram
ORDERING GUIDE
Models AD7741BN AD7741BR AD7741YR AD7742BN AD7742BR AD7742YR
Temperature Ranges -40C to +85C -40C to +85C -40C to +105C -40C to +85C -40C to +85C -40C to +105C
Package Descriptions Plastic DIP Small Outline Small Outline Plastic DIP Small Outline Small Outline
Package Options N-8 R-8 R-8 N-16 R-16A R-16A
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to GND . . . . . . . . -5 V to VDD + 0.3 V Digital Input Voltage to GND . . . . . . . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . -0.3 V to VDD + 0.3 V fOUT to GND . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Automotive (Y Version) . . . . . . . . . . . . . . -40C to +105C Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C Plastic DIP Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance (8 Lead) . . . . . . . . . . . . . 125C/W JA Thermal Impedance (16 Lead) . . . . . . . . . . . . 117C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C SOIC Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance (8 Lead) . . . . . . . . . . . . . 157C/W JA Thermal Impedance (16 Lead) . . . . . . . . . . . . 125C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7741/AD7742 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7741/AD7742
AD7741 PIN FUNCTION DESCRIPTION
Pin No. 1 2 3
Mnemonic VDD GND CLKOUT
Function Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be adequately decoupled to GND. Ground reference point for all circuitry on the part. External Clock Output. When the master clock for the device is a crystal, the crystal is connected between CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source elsewhere in the system. External Clock Input. The master clock for the device can be provided in the form of a crystal or an external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the master clock may be as high as 6 MHz. This is the reference input to the core of the VFC and defines the span of the VFC. If this pin is left unconnected, the internal 2.5 V reference is used. Alternatively, a precision external reference (e.g., REF192) may be used to overdrive the internal reference. The internal bandgap reference has a high output impedance in order to allow it to be overdriven. The analog input to the VFC. It has an input range from 0 V to VREF. This input is buffered so it draws virtually no current from whatever source is driving it. Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typically consumes 15 A of current. Frequency Output. This pin provides the output of the synchronous VFC.
4
CLKIN
5
REFIN/OUT
6 7 8
VIN PD fOUT
PIN CONFIGURATION
VDD 1 GND 2
8
fOUT
PD TOP VIEW CLKOUT 3 (Not to Scale) 6 VIN
7
AD7741
CLKIN 4
5
REFIN/OUT
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AD7741/AD7742
AD7742 PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4-5 6
Mnemonic fOUT VDD GND A1, A0 CLKOUT
Function Frequency Output. This pin provides the output of the synchronous VFC. Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be adequately decoupled to GND. Ground reference point for all circuitry on the part. Address Inputs used to select the input channel configuration. External Clock Output. When the master clock for the device is a crystal, the crystal is connected between CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source elsewhere in the system. External Clock Input. The master clock for the device can be provided in the form of a crystal or an external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the master clock may be as high as 6 MHz. Control input which determines whether the device operates with differential bipolar analog input signals or differential unipolar analog input signals. 2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a reference to other parts of the system provided it is buffered first. This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V reference is required at this pin. This may be provided by connecting it directly to REFOUT or by using a precision external reference (e.g., REF192). Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to VIN4 or it is the positive input of a truly-differential input pair with respect to VIN2. Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to VIN4 or it is the negative input of a truly-differential input pair with respect to VIN1. Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with respect to VIN4. Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respect to VIN1 or VIN2 or it is the negative input of a truly-differential input pair with respect to VIN3. Gain Select input that controls whether the gain on the analog front-end is X1 or X2. Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typically consumes 25 A of current.
7
CLKIN
8 9 10
UNI/BIP REFOUT REFIN
11 12 13 14 15 16
VIN1 VIN2 VIN3 VIN4 GAIN PD
PIN CONFIGURATION
fOUT 1 VDD 2 GND 3 A1 4
16 PD 15 GAIN 14 VIN4
13 VIN3 TOP VIEW A0 5 (Not to Scale) 12 VIN2
AD7742
CLKOUT 6 CLKIN 7 UNI/BIP 8
11 VIN1 10 REFIN 9
REFOUT
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AD7741/AD7742
TERMINOLOGY
INTEGRAL NONLINEARITY GENERAL DESCRIPTION
For the VFC, Integral Nonlinearity (INL) is a measure of the maximum deviation from a straight line passing through the actual endpoints of the VFC transfer function. The error is expressed in % of the frequency span: Frequency Span = fOUT(max) - fOUT(min)
OFFSET ERROR
The AD7741/AD7742 are a new generation of CMOS synchronous Voltage-to-Frequency Converters (VFCs) that use a charge-balance conversion technique. The AD7741 is a singlechannel version and the AD7742 is a multichannel version. The input voltage signal is applied to a proprietary programmable gain front-end based around an analog modulator that converts the input voltage into an output pulse train. The parts also contain an on-chip +2.5 V bandgap reference and operate from a single +5 V supply. A block diagram of the AD7742 is shown in Figure 2.
VIN1 VIN2 INPUT MUX SWITCHED CAPS INTEGRATOR SWITCHED CAPS COMPARATOR fOUT
This is a measure of the offset error of the VFC. Ideally, the minimum output frequency (corresponding to minimum input voltage) is 5% of fCLKIN The deviation from this value is the offset error. It is expressed in terms of the error referred to the input voltage. It is expressed in mV.
GAIN ERROR
VIN3 VIN4
This is a measure of the span error of the VFC. The gain is the scale factor that relates the input VIN to the output fOUT. The gain error is the deviation in slope of the actual VFC transfer characteristic from the ideal expressed as a percentage of the full-scale span.
OFFSET ERROR DRIFT
Figure 2. AD7742 Block Diagram
Input Amplifier Stage
This is a measure of the change in Offset Error with changes in temperature. It is expressed in V/C.
GAIN ERROR DRIFT
The buffered input stage for the analog inputs presents a high impedance, allowing significant external source impedances. The four analog inputs (VIN1 through VIN4) each have a voltage range from +0.5 V to VDD - 1.75 V. This is an absolute voltage range and is relative to the GND pin. In the case of the AD7742 multichannel part, a differential multiplexer switches one of the differential input channels to the VFC modulator. The multiplexer is controlled by two pins, A1 and A0. See Table I for channel configurations.
Table I. AD7742 Input Channel Selection
This is a measure of the change in Gain Error with changes in temperature. It is expressed in (ppm of span)/C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the VFC is affected by changes in the supply voltage. Again, this error is referred to the input voltage. The input voltage is kept constant and the VDD supply is varied 5%. The ratio of the apparent change in input voltage to the change in VDD is measured in dBs.
CHANNEL-TO-CHANNEL ISOLATION
A1 0 0 1 1
A0 0 1 0 1
VIN(+) VIN1 VIN2 VIN3 VIN1
VIN(-) VIN4 VIN4 VIN4 VIN2
Type Pseudo Differential Pseudo Differential Full Differential Full Differential
This is a ratio of the amplitude of the signal at the input of one channel to a sine wave on the input of another channel. It is measured in dBs.
COMMON-MODE REJECTION
Analog Input Ranges
For the AD7742, the output frequency should remain unchanged provided the differential input remains unchanged although its common-mode level may change. The CMR is the ratio of the apparent change in differential input voltage to the actual change in common-mode voltage. It is expressed in dBs.
The AD7741 has a unipolar single-ended input channel whereas the AD7742 contains four input channels which may be configured as two fully differential channels or as three pseudodifferential channels. The AD7742 also has a X1/X2 gain option on the front end. The channel and gain settings are pin-programmable. The AD7742 uses differential inputs to provide common-mode noise rejection (i.e., the converted result will correspond to the differential voltage between the two inputs). The absolute voltage on both inputs must lie between +0.5 V and VDD -1.75 V.
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AD7741/AD7742
Table II. AD7741/AD7742 Input Range Selection
UNI/BIP N/A 0 0 1 1
GAIN N/A 0 1 0 1
Gain, G X1 X1 X2 X1 X2
VIN(Min) fOUT = 0.05 fCLKIN 0 -VREF -VREF/2 0 0
VIN(Max) fOUT = 0.45 fCLKIN +VREF +VREF +VREF/2 +VREF +VREF/2
OUTPUT FREQUENCY fOUT
Part AD7741 AD7742 AD7742 AD7742 AD7742
As can be seen from Table II, the AD7741 has one input range configuration whereas the AD7742 has unipolar/bipolar as well as gain options depending on the status of the GAIN and UNI/BIP pins. The transfer function for the AD7741 is shown in Figure 3. Figure 4 shows the AD7742 transfer function for unipolar input range configuration while the AD7742 transfer function for bipolar input range configuration is shown in Figure 5.
OUTPUT FREQUENCY fOUT
fOUTMAX (0.45 fCLKIN)
fOUTMIN (0.05 fCLKIN) VREF GAIN VREF GAIN DIFFERENTIAL INPUT VOLTAGE
-
fOUTMAX (0.45 fCLKIN)
+
Figure 5. AD7742 Transfer Characteristic for Bipolar Differential Input Range: -VREF/Gain to +VREF/Gain; the common-mode range must be between +0.5 V and VDD - 1.75 V. UNI/BIP pin tied to GND.
VFC Modulator
0 REFIN INPUT VOLTAGE VIN
fOUTMIN (0.05 fCLKIN)
Figure 3. AD7741 Transfer Characteristic for Input Range from 0 to VREF
OUTPUT FREQUENCY fOUT
The analog input signal to the AD7741/AD7742 is continuously sampled by a switched capacitor modulator whose sampling rate is set by a master clock input that may be supplied externally or by a crystal-controlled on-chip clock oscillator. However, the input signal is buffered on-chip before being applied to the sampling capacitor of the modulator. This isolates the sampling capacitor charging currents from the analog input pins. This system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero, by balancing charge injected by the input voltage with charge injected by the VREF. The output of the comparator provides the digital input for the 1-bit DAC, so that the system functions as a negative feedback loop that tries to minimize the difference signal (see Figure 6).
CLK INTEGRATOR COMPARATOR
fOUTMAX (0.45 fCLKIN)
fOUTMIN (0.05 fCLKIN) 0 + VREF GAIN DIFFERENTIAL INPUT VOLTAGE
INPUT + -
+ -
+VREF
1-BIT STREAM
Figure 4. AD7742 Transfer Characteristic for Unipolar Differential Input Range: 0 V to VREF/Gain; the input common-mode range must be between +0.5 V and VDD - 1.75 V. UNI/BIP pin tied to VDD.
-VREF
Figure 6. AD7741/AD7742 Modulator Loop
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AD7741/AD7742
The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. The output is a fixed-width pulse whose frequency depends on the analog input signal. The input voltage is offset internally so that a full-scale input gives an output frequency of 0.45 fCLKIN and zero-scale input gives an output frequency of 0.05 fCLKIN. The output allows simple interfacing to either standard logic families or opto-couplers. The clock high period controls the pulsewidth of the frequency output. The pulse is initiated by the edge of the clock signal. The delay time between the edge of the clock and the edge of the frequency output is typically 9 ns. Figure 7 shows the waveform of this frequency output. After power-up, or if there is a step change in input voltage, there is a settling time that must elapse before valid data is obtained. This is typically 2 CLKIN cycles on the AD7742 and 10 CLKIN cycles on the AD7741.
fCLKIN
AD7741/AD7742
TO OTHER CIRCUITRY 5M
CLKIN C1
CLKOUT C2
Figure 8. On-Chip Oscillator
The on-chip oscillator circuit also has a start-up time associated with it before it oscillates at its correct frequency and correct voltage levels. The typical start-up time for the circuit is 5 ms (with a 6.144 MHz crystal). The AD7741/AD7742 master clock appears on the CLKOUT pin of the device. The maximum recommended load on this pin is one CMOS load. When using a crystal to generate the AD7741/ AD7742 clock it may be desirable to then use this clock as the clock source for the system. In this case it is recommended that the CLKOUT signal be buffered with a CMOS buffer before being applied to the rest of the circuit.
Reference Input
fOUT = fCLKIN/4 VIN = VREF/2 fOUT = fCLKIN/10 VIN = VREF/8
fOUT = fCLKIN*3/20 VIN = VREF/4 6 TCLK 7 TCLK
AVERAGE fOUT IS fCLKIN *3/20 BUT THE ACTUAL PULSE STREAM VARIES BETWEEN fCLKIN/6 AND fCLKIN/7
Figure 7. AD7741/AD7742 Frequency Output Waveforms
Clock Generation
As distinct from the asynchronous VFCs which rely on the stability of an external capacitor to set their full-scale frequency, the AD7741/AD7742 uses an external clock to define the full-scale output frequency. The result is a more stable, more linear transfer function and also allows the designer to determine the system stability and drift based upon the external clock selected. A crystal oscillator may also be used if desired. The AD7741/AD7742 requires a master clock input, which may be an external CMOS-compatible clock signal applied to the CLKIN pin (CLKOUT not used). Alternatively, a crystal of the correct frequency can be connected between CLKIN and CLKOUT, when the clock circuit will function as a crystal controlled oscillator. Figure 8 shows a simple model of the onchip oscillator.
The AD7741/AD7742 performs conversion relative to an applied reference voltage that allows easy interfacing to ratiometric systems. This reference may be applied using the internal 2.5 V bandgap reference. For the AD7741, this is done by simply leaving REFIN/OUT unconnected. For the AD7742, REFIN is tied to REFOUT. Alternatively, an external reference, e.g., REF192 or AD780, may be used. For the AD7741, this is connected to REFIN/OUT and will overdrive the internal reference. For the AD7742, it is connected directly to the REFIN pin. While the internal reference will be adequate for most applications, power supply rejection and overall regulation may be improved through the use of an external precision reference. The process of selecting an external voltage reference should include consideration of drive capability, initial error, noise and drift characteristics. A suitable choice would be the AD780 or REF192.
Power-Down Mode
The low power standby mode is initiated by taking the PD pin low, which shuts down most of the analog and digital circuitry. This reduces the power consumption to 185 W max.
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AD7741/AD7742
APPLICATIONS
The basic connection diagram for the part is shown in Figure 9. In the connection diagram shown, the AD7742 analog inputs are configured as fully differential, bipolar inputs with a gain of 1. A quartz crystal provides the master clock source for the part. It may be necessary to connect capacitors (C1 and C2 in the diagram) on the crystal to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors will vary depending on the manufacturer's specifications.
+5V
VIN
AD7741
fOUT
COUNTER
TO
P
CLKIN
GATE SIGNAL FREQUENCY DIVIDER
CLOCK GENERATOR
Figure 10. A/D Conversion Using the AD7741 VFC
4096x TCLOCK fCLKIN
VIN1 DIFF INPUT 1 VIN2 VIN3 DIFF INPUT 2 VIN4 A0 CHANNEL SELECT A1
VDD
PD REFOUT REFIN
fOUT
AD7742
fOUT
GATE
GND UNI/BIP GAIN
TGATE
Figure 11. Waveforms in an A/D Converter Using a VFC
CLKIN C1
CLKOUT C2
The clock frequency and the gate time determine the resolution of such an ADC. If 12-bit resolution is required and fCLKIN is 5 MHz (therefore, fOUT max is 2.25 MHz), the minimum gate time required is calculated as follows: N counts at Full Scale (2.25 MHz) will take (N/2.25 x 106) seconds = minimum gate time. N is the total number of codes for a given resolution; 4096 for 12 bits minimum gate time = (4096/2.25 x 106) sec = 1.820 ms. Since TGATE x fOUT max = number of counts at full scale, a faster conversion with the same resolution can be performed with a higher fOUT max. This high fOUT max (3 MHz) is a main feature of the AD7741/AD7742. If the output frequency is measured by counting pulses gated to a signal which is derived from the clock, the clock stability is unimportant and the device simply performs as a voltagecontrolled frequency divider, producing a high resolution ADC. The inherent monotonicity of the transfer function and wide range of input clock frequencies allows the conversion time and resolution to be optimized for specific applications. There is another parameter is taken into account when choosing the length of the gate interval. Because the integration period of the system is equal to the gate interval, any interfering signal can be rejected by counting for an integer number of periods of the interfering signal. For example, a gate interval of 100 ms will give normal-mode rejection of 50 Hz and 60 Hz signals.
Figure 9. Basic Connection Diagram
A/D Conversion Techniques Using the AD7741/AD7742
When used as an ADC, VFCs provide certain advantages including accuracy, linearity and being inherently monotonic. The AD7741/AD7742 has a true integrating input which smooths out noise peaks. The most popular method of using a VFC in an A/D system is to count the output pulses of fOUT for a fixed gate interval (see Figure 10). This fixed gate interval should be generated by dividing down the clock input frequency. This ensures that any errors due to clock jitter or clock frequency drift are eliminated. The ratio of the fOUT to the clock frequency is what is important here, not the absolute value of fOUT. The frequency division can be done by a binary counter where fCLKIN is the CLK input. Figure 11 shows the waveforms of fCLKIN, fOUT and the Gate signal. A counter counts the rising edges of fOUT while the Gate signal is high. Since the gate interval is not synchronized with fOUT, there is a possibility of a counting inaccuracy. Depending on fOUT, an error of one count may occur.
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AD7741/AD7742
Isolation Applications Power Supply Bypassing and Grounding
In addition to analog-to-digital conversion, the AD7741/AD7742 can be used in isolated analog signal transmission applications. Due to noise, safety requirements or distance, it may be necessary to isolate the AD7741/AD7742 from any controlling circuitry. This can easily be achieved by using opto-isolators, which will provide isolation in excess of 3 kV. Opto-electronic coupling is a popular method of isolated signal coupling. In this type of device, the signal is coupled from an input LED to an output photo-transistor, with light as the connecting medium. This technique allows dc to be transmitted, is extremely useful in overcoming ground loops between equipment, and is applicable over a wide range of speeds and power. The analog voltage to be transmitted is converted to a pulse train using the VFC. An opto-isolator circuit is used to couple this pulse train across an isolation barrier using light as the connecting medium. The input LED of the isolator is driven from the output of the AD7741/AD7742. At the receiver side, the output transistor is operated in the photo-transistor mode. The pulse train can be reconverted to an analog voltage using a frequency-to-voltage converter; alternatively, the pulse train can be fed into a counter to generate a digital signal. The analog and digital sections of the AD7741/AD7742 have been designed to allow operation from a single-ended power source, simplifying its use with isolated power supplies. Figure 12 shows a general purpose VFC circuit using a low cost opto-isolator. A +5 V power supply is assumed for both the isolated (+5 V isolated) and local (+5 V local) supplies.
+5V VCC
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board housing the AD7741/AD7742 should be designed so the analog and digital sections are separated and confined to certain areas of the board. To minimize capacitive coupling between them, digital and analog ground planes should only be joined in one place, close to the DUT and should not overlap. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7742 to avoid noise coupling. The power supply lines to the AD7742 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and clock signals should never be run near analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effect of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while the signal traces are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled to GND with surface mount capacitors, 10 F in parallel with 0.1 F located as close to the package as possible, ideally right up against the device. The lead lengths on the bypass capacitor should be as short as possible. It is essential that these capacitors be placed physically close to the AD7741/AD7742 to minimize the inductance of the PCB trace between the capacitor and the supply pin. The 10 F are the tantalum bead type and are located in the vicinity of the VFC to reduce lowfrequency ripple. The 0.1 F capacitors should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Additionally, it is beneficial to have large capacitors (> 47 F) located at the point where the power connects to the PCB.
VDD R IN
OPTOCOUPLER
AD774x
fOUT GND2
GND1
ISOLATION BARRIER
Figure 12. Opto-Isolated Application
REV. 0
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AD7741/AD7742
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
8-Lead SO (R-8)
0.1968 (5.00) 0.1890 (4.80)
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)
8
5 4
1
4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.100 (2.54) BSC
0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.102 (2.59) 0.094 (2.39) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 8 0
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
16-Lead Plastic DIP (N-16)
0.840 (21.34) 0.745 (18.92)
16 1 9 8
16-Lead Narrow Body SO (R-16A)
0.3937 (10.00) 0.3859 (9.80)
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
0.1574 (4.00) 0.1497 (3.80)
16 1
9 8
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
0.0098 (0.25) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 PLANE 0.0138 (0.35) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
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REV. 0
PRINTED IN U.S.A.
C3601-8-5/99

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